Field of the Invention
The invention relates to a method and a device for reducing the number of addresses of faulty memory cells of a memory array. These addresses are determined when the operability of the memory cells of the memory array is checked. The device and the method are used in particular in a semiconductor memory with a memory cell field which is provided in the form of a matrix.
When the operability of memory cells of a semiconductor memory is checked, a large number of addresses which identify faulty memory cells is determined due to the large number of memory cells. The large number of addresses requires a large memory area and a considerable outlay for storing and processing the addresses.